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Features
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Pulse-width Modulation up to 2 kHz Clock Frequency Protection against Short-circuit, Load-dump Overvoltage and Reverse VS Duty-cycle 0 to 100% Continuously Output Stage for Power MOSFET Interference and Damage Protection According to VDE 0839 and ISO/TR 7637/1 Charge-pump Noise Suppressed Ground-wire Breakage Protection
Description
The U6084B is a PWM-IC with bipolar technology designed for the control of an N-channel power MOSFET used as a high-side switch. The IC is ideal for use in the brightness control (dimming) of lamps such as in dashboard applications. For constant brightness, the preselected duty-cycle can be reduced automatically as a function of the supply voltage. Figure 1. Block Diagram with External Circuit
C5 16 9 Short circuit latch monitoring 5 RC oscillator 6 C1 PWM Charge 13 pump Logic 3 Control input Output C3 47 nF 14 11 Current monitoring + short circuit detection 12 Rsh VBatt
PWM Power Control with Automatic Duty-cycle Reduction U6084B
VS
47 k
C2
Duty cycle range 0-100%
Duty cycle reduction 4
Voltage monitoring 1
Enable/ disable 2
150
R3 Ground
Rev. 4677B-AUTO-02/04
Pin Configuration
Figure 2. Pinning
GND EN/DIS VI REDUCT NC OSC NC NC
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VS NC OUTPUT 2 VS SENSE DELAY NC LATCH
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol GND EN/DIS VI REDUCT NC OSC NC NC LATCH NC DELAY SENSE 2VS OUTPUT NC VS Function IC ground Enable/disable Control input (duty cycle) Duty cycle reduction Attenuation Oscillator Not connected Not connected Status short-circuit latch Not connected Short-circuit protection delay Current sensing Voltage doubler Output Not connected Supply voltage VS
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4677B-AUTO-02/04
U6084B
Functional Description
Pin1 - GND
Ground-wire Breakage To protect the FET in case of ground-wire breakage, a 820 k resistor between gate and source is recommended to provide proper switch-off conditions. The dimmer can be switched on or off, with pin 2, independently of the set duty cycle. Table 1. Pin 2 Function
V2 Approximately > 0.7 V or open < 0.7 V or connected to pin 1 Function Disable Enable
Pin 2 - Enable/Disable
Pin 3 - Control Input
The pulse width is controlled by means of an external potentiometer (47 k). The characteristic (angle of rotation/duty cycle) is linear. The duty cycle be varied from 0 to 100%. It is possible to further restrict the duty cycle with resistors R1 and R2 (see Figure 3 on page 8). Pin 3 is protected against short-circuit to VBatt and ground GND (VBatt 16.5 V).
Pin 4 - Duty Cycle Reduction
With pin 4 connected according to Figure 3 on page 8, the set duty cycle is reduced to VBatt 12.5 V. This causes a power reduction in the FET and in the lamps. In addition, the brightness of the lamps is largely independent of the supply voltage range, VBatt = 12.5 to 16 V. The rise and fall time (tr, tf) of the lamp voltage can be limited to reduce radio interference. This is done with an integrator which controls a power MOSFET as source follower. The slope time is controlled by an external capacitor C4 and the oscillator current (see Figure 3 on page 8). Calculation:
C4 t f = t r = VBatt x -------I osc
Output Slope Control
With VBatt = 12 V, C4 = 470 pF and Iosc = 40 A, we thus obtain a controlled slope of
470 pF t f = t r = 12 V x ----------------- x 141 s 40 A
Pin 5 - Attenuation Pin 6 - Oscillator
Capacitor C4 connected to pin 5 damps oscillation tendencies. The oscillator determines the frequency of the output voltage. This is defined by an external capacitor, C2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double current, 2 x I, from the charging current. The capacitor, C2 , is thus discharged by the current, I, until the lower switching threshold is reached. The second source is then switched off again and the procedure starts once more.
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4677B-AUTO-02/04
Example for Oscillator Frequency Calculation
V T100 = VS x 1 = ( V Batt - IS x R 3 ) x 1 V T<100 = VS x 2 = ( V Batt - IS x R 3 ) x 2 V TL = V S x 3 = ( V Batt - IS x R 3 ) x 3
where VT100 = High switching threshold 100% duty cycle VT<100 = High switching threshold < 100% duty cycle VTL = Low switching threshold 1, 2 and 3 are fixed values The above mentioned threshold voltages are calculated for the following values given in the datasheet. VBatt = 12 V, IS = 4 mA, R3 = 150 , 1 = 0.7, 2 = 0.67 and 3 = 0.28. VT100 = (12 V - 4 mA x 150 ) x 0.7 8 V VT<100 = 11.4 V x 0.67 = 7.6 V VTL = 11.4 V x 0.28 = 3.2 V For a duty cycle of 100%, the oscillator frequency, f, is as follows:
I osc f = ----------------------------------------------------------- where C2 = 22 nF and Iosc = 40 A 2 x ( V T100 - VTL ) x C 2
Therefore:
40 A f = ------------------------------------------------------------------ = 189 Hz 2 x ( 8 V - 3.2 V ) x 22 nF
For a duty cycle of less than 100%, the oscillator frequency, f, is as follows:
I osc f = ---------------------------------------------------------------------------------------------------------2 x ( V T<100 - V TL ) x C 2 + 4 x V Batt x C 4
where C4 = 470 pF
40 A f = ------------------------------------------------------------------------------------------------------------------------------ = 185 Hz 2 x ( 7.6 V - 3.2 V ) x 22 nF + 4 x 12 V x 470 pF
A selection of different values of C2 and C4 provides a range of oscillator frequencies from 10 to 2000 Hz.
Pins 7, 8, 10 and 15 Pin 9 - Status Short Circuit Latch
Not connected. The status of the short-circuit latch can be monitored via pin 9 (open collector output). Table 2. Pin 9 Function
Pin 9 L H Function Short-circuit detected Not short-circuit detected
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U6084B
4677B-AUTO-02/04
U6084B
Pins 11 and 12 - Short-circuit Protection and Current Sensing
Short-circuit Detection and Time Delay td The lamp current is monitored by means of an external shunt resistor. If the lamp current exceeds the threshold for the short-circuit detection circuit (VT2 90 mV), the duty cycle is switched over to 100% and capacitor C5 is charged by a current source of 20 A (Ich - Idis). The external FET is switched off after the cut-off threshold (VT11) is reached. Renewed switching on the FET is possible only after a power-on reset. The current source, Idis, ensures that capacitor C5 is not charged by parasitic currents. Capacitor C5 is discharged by Idis to typ. 0.7 V. Time delay, td, is as follows:
( V 11 - 0.7 V ) t d = C 5 x --------------------------------( Ich - Idis )
With C5 = 330 nF and VBatt = 12 V, we have
( 9.8 V - 0.7 V ) t d = 330 nF x -------------------------------------- = 150 ms 20 A
Current Limitation
The lamp current is limited by a control amplifier that protects the external power transistor. The voltage drop across an external shunt resistor acts as the measured variable. Current limitation takes place for a voltage drop of VT1 100 mV. Owing to the difference VT - VT2 10 mV, current limitation occurs only when the short-circuit detection circuit has responded. After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the supply voltage capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is switched on for the first time.
Pins 13 and 14 - Charge Pump and Output
Pin 14 (output) is suitable for controlling a power MOSFET. During the active integration phase, the supply current of the operational amplifier is mainly supplied by capacitor C3 (bootstrapping). Additionally, a trickle charge is generated by an integrated oscillator (f13 400 kHz) and a voltage doubler circuit. This permits a gate voltage supply at a duty cycle of 100%.
Pin 16 - Supply Voltage, Vs or VBatt
Undervoltage Detection In the event of voltages of approximately VBatt < 5.0 V, the external FET is switched off and the latch for short-circuit detection is reset. A hysteresis ensures that the FET is switched on again at approximately VBatt 5.4 V. Overvoltage Detection Stage 1 If overvoltages of VBatt > 20 V (typically) occur, the external transistor is switched off and switched on again at VBatt < 18.5 V (hysteresis). If VBatt > 28.5 V (typically), the voltage limitation of the IC is reduced from 26 V to 20 V. The gate of the external transistor remains at the potential of the IC ground, thus producing voltage sharing between the FET and lamps in the event of overvoltage pulses (e.g., load-dump). The short-circuit protection is not in operation. At VBatt < 23 V, the overvoltage detection stage 2 is switched off.
Stage 2
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4677B-AUTO-02/04
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Parameters Junction temperature Ambient temperature range Storage temperature range Symbol Tj Tamb Tstg Value 150 -40 to +110 -55 to +125 Unit C C C
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 120 Unit K/W
Electrical Characteristics
Tamb = -40 to +110C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 1). All other values refer to pin GND (pin 1).
Parameters Current consumption Supply voltage Stabilized voltage Battery undervoltage detection Battery Overvoltage Detection Stage 1: Stage 2: Stabilized voltage Short-circuit Protection Short-circuit current limitation Short-circuit detection Delay Timer Short-circuit Detection Switched off threshold Charge current Discharge current Capacitance current Output short-circuit latch Saturation voltage Notes: I5 = Ich - Idis Pin 9 I9 = 100 A Vsat 150 350 mV Test Conditions Pin 16 Overvoltage detection, stage 1 IS = 10 mA, pin 16 - on - off Pin 2 - on - off - on - off IS = 30 mA, pin 16 Pin 12 VT1 = VS - V12 VT2 = VS - V12 Pin 11 VT11 = VS - V11 VT11 Ich Idis I5 13 9.5 9.8 23 3 20 27 10.1 V A A mA VT1 VT2 VT1 - VT2 85 75 3 100 90 10 120 105 30 mV mV mV VBatt VBatt VZ 18.3 16.7 25.5 19.5 18.5 20.0 18.5 28.5 23.0 20.0 21.7 20.3 32.5 26.5 21.5 V V V Symbol IS VBatt VS VBatt 24.5 4.4 4.8 5.0 5.4 Min. Typ. Max. 6.8 25 27.0 5.6 6.0 Unit mA V V V
1. Reference point is battery ground
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U6084B
4677B-AUTO-02/04
U6084B
Electrical Characteristics (Continued)
Tamb = -40 to +110C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 1). All other values refer to pin GND (pin 1).
Parameters Voltage Doubler Voltage Oscillator frequency Internal voltage limitation Gate Output I13 = 5 mA (whichever is lower) Pin 14 Low level Voltage VBatt = 16.5 V, Tamb = 110C, R3 = 150 High level, duty cycle 100% Current Enable/Disable Current Duty Cycle Reduction Z-voltage Oscillator Frequency Threshold cycle Upper Pin6 V T100 V 14 = High, 1 = -------------VS V T<100 V 14 = Low, 2 = ---------------VS V TL 3 = -------VS Oscillator current Frequency tolerance Notes: VBatt = 12 V C4 open, C2 = 470 nF, duty cycle = 50% f 1 10 0.68 0.7 2000 0.72 Hz V14 = Low level V14 = High level, I13 > I14 Pin 2 V2 = 0 V Pin 4 I4 = 500 A V4 6.9 7.4 8.0 V I2 -20 -40 -60 A V14 I14 1.0 -1.0 V13 mA V14 0.35 0.70 0.95 1.5(1) V Test Conditions Pin 13 Duty cycle 100% V13 f13 V13 V13 2 VS 280 26 (VS+14) 400 27.5 (VS+15) 520 30.0 (VS+16) kHz V Symbol Min. Typ. Max. Unit
Lower
2
0.65
0.67
0.69
3 Iosc f
0.26 26 6.0
0.28 40 9.9
0.3 54 13.5 A Hz
1. Reference point is battery ground
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Figure 3. Application
8
C5 330 nF VBatt 5 VS VS VS VS + + Current limiting I + Oscillator Idis + Reset 2I Switch - on delay 13 C3 47 nF Overvoltage monitoring stage 2 VS Reset 820 k Low voltage monitoring 2 1 7 NC 150 R3 Ground 8 NC NC 10 15 NC Load RL 14 Reset Voltage doubler VS 10 mV Ich 90 mV C4 47 pF RSh VS VS 11 16 9 12 Overvoltage monitoring stage 1
U6084B
100
6
C1
47 F
R1
C2
22 nF
47 k
3
30 k
4
R2
VS
C6
VS
4677B-AUTO-02/04
U6084B
Ordering Information
Extended Type Number U6084B-FP Package SO16 Remarks -
Package Information
Package SO16
Dimensions in mm
10.0 9.85 5.2 4.8 3.7
1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
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Revision History
Changes from Rev. 4677A - 02/03 to Rev. 4677B - 02/04
Please note that the referring page numbers in this section are referred to the specific revision mentioned, not to this document. 1. Block Diagram on page 1 changed. 2. New heading rows at Table "Absolute Maximum Ratings" on page 6 added.
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4677B-AUTO-02/04
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4677B-AUTO-02/04

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